There are numerous applications in which it is either necessary or desirable to delay an applied pulse signal. For example, in circuits which perform a plurality of operations in a predetermined time sequence in response to a single input pulse signal, a plurality of timer circuits has heretofore most often been utilized to insure that each operation occurs at a predetermined time interval after changes of state in the input pulse signal. In many applications it is also necessary, in addition to delaying operation of a function, to delay termination of that function. For example, it may be necessary to delay initiating a particular function, i.e., enabling or operating a relay or the like for a predetermined interval after application of an input pulse signal and also to delay terminating a circuit function, i.e., disabling or releasing the relay by a similar or different predetermined time interval after the input pulse signal has terminated. The initiation and termination delay intervals are commonly referred to as operate and release intervals, respectively.
Many circuits are known which introduce time delays to applied pulse signals. These circuits vary in complexity from the simple monostable multivibrator to more complex circuit arrangements for precisely generating a plurality of delayed pulse signals. In applications requiring both operate and release delay intervals it has been common practice to employ a separate timer for generating each of the desired delay intervals. Consequently, both circuit complexity and cost are increased. Another limitation of many known timer circuits is the inability to maintain the desired timing sequence when the applied input pulse signal is momentarily interrupted because of spurious discontinuities, i.e., noise, gaps or the like.
One analog time circuit which has been advantageously employed to overcome limitations of prior analog timers is disclosed in U.S. Pat. No. 3,889,197, issued to T. G. Duff on June 10, 1975. This prior timer employs an operational amplifier integrator circuit and a voltage comparator circuit to obtain desired operate and release delay intervals. Basically, the integrator integrates an applied input pulse signal while the comparator detects the voltage at a prescribed circuit point of the integrator to determine when the integrator has reached a saturation point. Desired time delays are obtained by setting the integrator time constant to yield a corresponding integration rate. Some degree of insensitivity to spurious discontinuities in the input signal is obtained by employing similar integration rates for both positive and negative input signals. However, in applications where the release time must be substantially shorter than the operate time, the release integration rate, i.e., response to a negative input, must be substantially shorter than the operate integration rate, i.e., response to a positive input. Consequently, when gaps are present in the input signal, the integrator may repetitively return to its initial condition thereby causing pulse width and pulse position errors in the timer output. Indeed, in many instances the integrator may not reach saturation, thereby not yielding any indication of the presence of input pulse signals.
One analog time circuit which overcomes some of the limitations of the prior Duff circuit is disclosed in U.S. Pat. No. 4,001,698 issued to R. R. Allred on Jan 4, 1977. The circuit disclosed in the Allred patent is an improvement over the prior Duff timer. In the Allred timer, the effects of gaps and the like in an input pulse signal are minimized by advantageously varying the integrator integration in accordance with signals generated internal to the timer circuit. Specifically, the discharge time constant, i.e., negative integration rate, is controlled to be a significantly longer time constant during the so-called operate timing interval. Consequently, the integrator is somewhat inhibited from returning to its initial condition because of gaps or the like in the applied input signal while still having a relatively short release time.
Although the prior known analog timer circuits may perform satisfactorily in numerous applications, they still employ standard resistor-capacitor (RC) timing arrangements requiring the use of capacitors and the like which are undesirable for certain integrated circuit implementations. Moreover, the integrator circuits are still responsive to the applied input signal and gaps therein which may cause undue pulse width and pulse position errors in the resulting output pulse signal. Furthermore, with the advent of large-scale integration it now becomes highly desirable to implement the operate/release timing functions utilizing digital techniques.
One prior known operate/release timer which is implemented by employing digital circuit techniques is disclosed in U.S. Pat. No. 3,700,821 issued to B. R. Savage on Oct. 24, 1972. The Savage arrangement employs two digital up/down counters and associated logic elements to obtain desired operate and release intervals. Specifically, the operate timer employs a digital up/down counter which is essentially the equivalent of an analog integrator. That is to say, the counter counts up, i.e., integrates in a first or positive sense in response to a pulse signal being present, for example, a high state input representative of a logical "1", and counts down, i.e., integrates in a second or negative sense in response to the pulse signal being absent, for example, a low state input representative of a logical "0". The counter must reach a predetermined count before an output pulse is generated. Once the input pulse signal is terminated the release counter begins counting to determine the release interval. Upon the release counter reaching a predetermined count, the operate timer is cleared to its initial condition. Since in the Savage circuit both the operate and release time functions are realized by employing up/down counters which are essentially integrators they too respond to momentary discontinuities in the applied pulse signal. Consequently, pulse position and pulse width errors result in the output pulse signal when gaps, breaks and the like appear in the applied input pulse signals. Additionally, the use of two counter circuits and associated logic to realize the operate and release timer functions requires undue duplication resulting in inefficient use of circuit components.
Furthermore, all of the known prior analog and digital timer circuit arrangements have been designed for specific applications. That is, the circuit component values and logic arrangements are fixed by design for a given application and are not readily alterable. Thus, a circuit change is required when employing the prior arrangements in different applications. This, in turn, requires maintenance of a larger inventory of both replacement and new parts, which is undesirable from an economic standpoint.